ARM RISC philosophy

It is interesting how ARM does not take the RISC philosophy too far. Yes, it does believe in single simple instructions that execute in one CPU cycle. But it does allow you to have complex instructions. For example, instructions that allow you to operate on multiple memory locations - possibly contiguous. The instruction may be a simple STR and does fit into 32 bits with the op-code + operand, but it may take longer than one CPU cycle to execute. This is ok - because ARM does not take RISC too far.

Also, the load-store architecture is cool. This is to guarantee that processing instructions always operate on registers - never directly on memory. Memory access is slow, it is better to have instructions that access memory work separately. This also allows some pipelining - because it may be possible that you issue a LDR on one instruction, while you are trying to execute a non-data dependent instruction at the same time.

Another point is code density - if ARM took the RISC architecture too seriously, then the code density would take a hit, because each instruction requires 32 bits (at least in the ARM instruction set, ignoring the 16-bit Thumb set), so if you need a lot more instructions to say something, your code becomes that much bloated.